;************************************************************************* ;** MMU Configuration file ** ;** ** ;** this file is read on startup by the mmu.library and used to modify ** ;** the pre-calculated or scanned MMU table ** ;** ** ;** © 1999-2021 THOR Software, Thomas Richter ** ;************************************************************************* ; the current version of the MMU library knows six commands that can ; be used in this file: ; CLEARTTX clears all or parts of the transparent translation registers ; ADDMEM adds memory to the exec free list pool. BE WARNED, this command ; does NOT modify the MMU tables, this must be done by yourself ; SETCACHEMODE defines the MMU tables. ; DESCRIPTORCACHEINHIBIT defines whether the data cache should be disabled ; for the MMU descriptors. It's usually OFF meaning the cache will ; remain enabled. This is fine for the mmu.library, but certain ; hacks might require a ON argument here. Note that this means more ; work for the library. ; FOR executes a command only for a specific hardware expansion which is ; given by the manufacturer and product ID. ; CLEARMMU overrides the MMU configuration found by the library for selected ; parts of the configuration. ; ; All other commands are currently "external". The library will scan for ; these commands in "LIBS:mmu" and execute them on startup. These *are not* ; standard shell commands. They cannot be run from the shell, and shell ; commands cannot be started from this file. ; ClearTTx ;ignore all TTX registers if any. We don't need them. ;this will speed up the system for some machines. ; Remove the semicolon in the line below if you have to live with other MMU ; hacks that expect the MMU descriptors in non-cacheable memory. This is by ; default OFF, i.e. descriptors will be cachable. ; The library will work fine and will take all precautions for descriptors ; in the cache, but some third-party hacks might not. ;DescriptorCacheInhibit ON ; Remove the semicolon in the two lines below in case you encounter hangs or ; crashes with Zorro-II 16-Bit memory. It will disable caching for the Z-II ; area. Clearly, this is slower, but it will work, at least. ;Z2Burst off ; The following lines are strictly speaking not necessary. ; They will change and optimize the caching mode for graphics boards, ; but it will also work without them. ; ; The Picasso96 software will also optimize the MMU caching mode itself ; and therefore makes the following completely superfluous. ; CyberGraphics does not take these steps and might profit from the ; following. ; ; To speedup booting, you may remove all the lines of the boards ; you do not own. ; ; Altais For 18260 19 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;Retina Z3 For 18260 16 Z3 SetCacheMode {base+0x00c00000} 0x00400000 CacheInhibit NonSerial Imprecise ;Merlin For 2117 3 Z3 SetCacheMode {base+0x00c00000} 0x00400000 CacheInhibit NonSerial Imprecise For 2117 3 Z2 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;oMniBus, Size > 0x00100000 For 2181 0 BIG SetCacheMode {base+0x00c00000} 0x00200000 CacheInhibit NonSerial Imprecise ;Graffity Z2 For 2092 33 Z2 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;Graffity Z3 For 2092 33 Z3 SetCacheMode {base+0x00c00000} 0x00200000 CacheInhibit NonSerial Imprecise ;Domino For 2167 1 Z2 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;PicassoII For 2167 11 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;GVP Spectrum For 2193 1 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;Piccolo For 2195 5 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;Piccolo-SD64 Z2 For 2195 10 Z2 SetCacheMode {base} {size} CacheInhibit NonSerial Imprecise ;Piccolo-SD64 Z3 For 2195 10 Z3 SetCacheMode {base} 0x00400000 CacheInhibit NonSerial Imprecise ;VA2000 For 28014 1 SetCacheMode {base} 0x10000 Valid CacheInhibit IOSpace For 28014 1 SetCacheMode {base+0x10000} {size-0x10000} Valid CacheInhibit NonSerial Imprecise ;Cybervision Z3 For 8512 34 Z3 SetCacheMode {base} {size} Blank IOSpace For 8512 34 Z3 SetCacheMode {base} 0x01400000 Valid IOSpace CacheInhibit For 8512 34 Z3 SetCacheMode {base+0x01400000} 0x00c00000 Valid IOSpace CacheInhibit NonSerial Imprecise For 8512 34 Z3 SetCacheMode {base+0x02000000} 0x02000000 Valid IOSpace CacheInhibit ;CyberVision 3D For 8512 67 SetCacheMode {base} {size} Blank IOSpace For 8512 67 Z2 SetCacheMode {base} 0x00380000 Valid IOSpace CacheInhibit NonSerial Imprecise For 8512 67 Z2 SetCacheMode {base+0x00380000} 0x00080000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x04000000} 0x01000000 Valid IOSpace CacheInhibit NonSerial Imprecise For 8512 67 Z3 SetCacheMode {base+0x05000000} 0x00010000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x05800000} 0x00008000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x07000000} 0x00008000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x08000000} 0x00001000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x0c000000} 0x00010000 Valid IOSpace CacheInhibit For 8512 67 Z3 SetCacheMode {base+0x0c0e0000} 0x00001000 Valid IOSpace CacheInhibit ;Rainbow III For 2145 33 SetCacheMode {base} {size} Blank IOSpace For 2145 33 SetCacheMode {base} 0x00400000 Valid IOSpace CacheInhibit ;MK-III SCSI Hostadapter For 8512 100 SetCacheMode {base} {size} Valid IOSpace CacheInhibit ;Blizzard PPC SCSI Hostadapter For 8512 110 SetCacheMode {base} {size} Valid IOSpace CacheInhibit ; ; The following define areas for the CBM bridgeboards. These boards ; actually do not need the caching mode setup indicated below, but ; the buggy 32.xx and 33.xx janus.library and tools will. ; Therefore, remove the comments below if you *must* run these buggy ; versions. ; ;A2088 Bridgeboard ;For 513 1 SetCacheMode 0x00e00000 0x00180000 Valid IoSpace CacheInhibit ;A2286 Bridgeboard ;For 513 2 SetCacheMode 0x00e00000 0x00180000 Valid IoSpace CacheInhibit ;A2386 Bridgeboard ;For 513 103 SetCacheMode 0x00e00000 0x00180000 Valid IoSpace CacheInhibit ; now execute the GVPInit command in LIBS:mmu GVPInit ; that's all folks!